sinter IP cores are designed for integration into an SoC imaging pipeline to provide intra-frame noise reduction or compression de-blocking. Standard interfaces are for 8- or 10- bit RGB or YUV video, and custom handlers for camera raw image formats are also avaliable.
An efficient hardware implementation of the sinter algorithms enables video processing without frame memory and with low gate count. No CPU or DSP core is required, although the core is fully programmable via a TWI bus.