Engines

IP cores

Apical’s iridix cores have been designed for maximum performance at lowest LSI gate count and memory, and built  for easy integration into a typical camera or display imaging pipeline

They operate synchronously with the video signal and can support up to 1080p at full frame rate and 16 Megapixel still images.Supported image formats include YUV and RGB at both 8 and 10 bit depths.

Three principal versions are available:

Version
Application
 High
Highest image quality and performance. Full HD/  cinema/ professional camera applications
 Standard
Optimal balance between image quality and gate count/ memory usage. Well-suited to most display and camera applications
 Lite
Optimised for lowest gate count and power consumption. Suited to mobile display device applications

 

The core is fully programmable via a standard two-wire (i2c compatible) serial interface. Video or still image data is output synchronously in the same format as input. Standard image formats are support by default in the video interfaces module. Custom interfacing can be provided on request.

Versions are available handling Wide Dynamic Range sensor input

Top-level block schematic of iridix IP core

 Core features

  • Pixel by pixel contrast and colour correction
  • Still image processing up to 16 Megapixel
  • Real-time video up to full HD 1080p
  • Standard and custom video formats
  • Compact, low-power core
  • No external memory required
  • No frame delay
  • Core is fully programmable

  Related documents

iridix IP core datasheet (DSC)
iridix IP core datasheet (display)
iridix IP core datasheet (video)